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1/43 preliminary data august 2005 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. m25pe80 8 mbit, low voltage, page-erasable serial flash memory with byte-alterability, 50mhz spi bus, standard pin-out features summary industrial standard spi pin-out 8 mbits of page-erasable flash memory page write (up to 256 bytes) in 11ms (typical) page program (up to 256 bytes) in 1.2ms (typical) page erase (256 bytes) in 10ms (typical) sector erase (512 kbits) bulk erase (8 mbits) 2.7 to 3.6v single supply voltage spi bus compatible serial interface 50mhz clock rate (maximum) deep power-down mode 1 a (typical) electronic signature ? jedec standard two-byte signature (8014h) more than 100,000 write cycles more than 20 year data retention hardware write protection of the top sector (64kb) software write protection on a 64kbyte sector basis software write protection on a 4kbyte sub- sector basis for sector 0 and sector 15 figure 1. packages vdfpn8 (mp) 6 x 5mm (mlp8) 8 1 so8w (mw) 208 mils width
m25pe80 2/43 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. vdfpn and so connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 reset (reset ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 top sector lock (tsl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. bus master and memory devices on the spi bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 an easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 a fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 active power, standby power and deep power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . 8 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. software protection truth table (sectors 1 to 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. software protection scheme truth table (sectors 0 and 15) . . . . . . . . . . . . . . . . . . . . . 10 figure 6. software protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 7. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. write enable (wren) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/43 m25pe80 figure 9. write disable (wrdi) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 read identification (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7. read identification (rdid) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10.read identification (rdid) instruction se quence and data-out sequence . . . . . . . . . . 16 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11.read status register (rdsr) instruction sequence and data-out sequence . . . . . . . 17 read data bytes (read). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12.read data bytes (read) instruction sequence and data-out sequence . . . . . . . . . . . 18 read data bytes at higher speed (fast_read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13.read data bytes at higher speed (fast_read) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 read lock register (rdlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. lock register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14.read lock register (rdlr) instruction sequence and data-out sequence . . . . . . . . . 20 page write (pw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15.page write (pw) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 page program (pp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 16.page program (pp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 write to lock register (wrlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 17.write to lock register (wrlr) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. lock register in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 page erase (pe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 18.page erase (pe) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 sector erase (se) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 19.sector erase (se) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 bulk erase (be) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 20.bulk erase (be) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 deep power-down (dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 21.deep power-down (dp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 release from deep power-down (rdp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 22.release from deep power-down (rdp) instruction sequence. . . . . . . . . . . . . . . . . . . . 29 power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 23.power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10. power-up timing and vwi threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 initial delivery state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 11. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 12. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
m25pe80 4/43 figure 24.ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 15. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 25.serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 26.top sector lock setup and hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 27.output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 17. reset timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 28.reset ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 29.mlp8, 8-lead very thin dual flat package no lead, 6x5mm, package outline . . . . . . . 39 table 18. mlp8, 8-lead very thin dual flat package no lead, 6x5mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 30.so8 wide ? 8 lead plastic small outline, 208 mils body width, package outline . . . . . . 40 table 19. so8 wide ? 8 lead plastic small outline, 208 mils body width, mechanical data . . . . . . 40 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 20. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 21. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5/43 m25pe80 summary description the m25pe80 is an 8 mbit (1mb x 8) serial paged flash memory accessed by a high speed spi- compatible bus. the memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. the page write instruction consists of an integrated page erase cycle fol- lowed by a page program cycle. the memory is organized as 16 sectors, each con- taining 256 pages. each page is 256 bytes wide. thus, the whole memory can be viewed as con- sisting of 4096 pages, or 1,048,576 bytes. the memory can be erased a page at a time, using the page erase instruction, a sector at a time, us- ing the sector erase instruction, or as a whole, us- ing the bulk erase instruction. the memory can be write protected by either hardware or software, with a protection granulari- ty of either 64 kbytes (sector granularity) or 4 kbytes (sub-sector granularity inside sector 0 and sector 15 only). figure 2. logic diagram table 1. signal names figure 3. vdfpn and so connections note: 1. there is an exposed die paddle on the underside of the mlp8 package. this is pulled, internally, to v ss , and must not be allowed to be connected to any other voltage or signal line on the pcb. 2. see package mechanical section for package di- mensions, and how to identify pin-1. reset ai10779 s v cc m25pe80 v ss tsl q c d c serial clock d serial data input q serial data output s chip select tsl top sector lock reset reset v cc supply voltage v ss ground 1 ai10780 2 3 4 8 7 6 5 d v ss c reset q sv cc tsl m25pe80
m25pe80 6/43 signal description serial data output (q). this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). serial data input (d). this input signal is used to transfer data serially into the device. it receives in- structions, addresses, and the data to be pro- grammed. values are latched on the rising edge of serial clock (c). serial clock (c). this input signal provides the timing of the serial interface. instructions, address- es, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q ) changes after the falling edge of serial clock (c). chip select (s ). when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal read, program, erase or write cycle is in progress, the device will be in the standby mode (this is not the deep power-down mode). driving chip select (s ) low selects the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. reset (reset ). the reset (reset ) input provides a hardware reset for the memory. when reset (reset ) is driven high, the memory is in the normal operating mode. when reset (re- set ) is driven low, the me mory will enter the reset mode. in this mode, the output is high impedance. driving reset (reset ) low while an internal oper- ation is in progress will affe ct this operation (write, program or erase cycle) and data may be lost. top sector lock (tsl ). this input signal puts the device in the hardware protected mode, when top sector lock (tsl ) is connected to v ss , caus- ing the top 256 pages (upper addresses) of the memory to become read-only (protected from write, program and erase operations). when top sector lock (tsl ) is connected to v cc , the top 256 pages of memory behave like the other pages of memory.
7/43 m25pe80 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the fa lling edge of serial clock (c). the difference between the two modes, as shown in figure 5. , is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 4. bus master and memory devices on the spi bus note: the top sector lock (tsl ) signal should be driven, high or low as appropriate. figure 5. spi modes supported ai10741 bus master (st6, st7, st9, st10, others) spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) tsl rp tsl rp tsl rp ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
m25pe80 8/43 operating features sharing the overhead of modifying data to write or program one (or more) data bytes, two instructions are required: write enable (wren), which is one byte, and a page write (pw) or page program (pp) sequence, which consists of four bytes plus data. this is followed by the internal cy- cle (of duration t pw or t pp ). to share this overhead, the page write (pw) or page program (pp) instruction allows up to 256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at a time, pro- vided that they lie in consecutive addresses on the same page of memory. an easy way to modify data the page write (pw) instruction provides a con- venient way of modifying data (up to 256 contigu- ous bytes at a time), and simply requires the start address, and the new data in the instruction se- quence. the page write (pw) instruction is entered by driving chip select (s ) low, and then transmitting the instruction byte, three address bytes (a23-a0) and at least one data byte, and then driving chip select (s ) high. while chip select (s ) is being held low, the data bytes are written to the data buffer, starting at the address given in the third ad- dress byte (a7-a0). when chip select (s ) is driv- en high, the write cycle starts. the remaining, unchanged, bytes of the data buffer are automati- cally loaded with the values of the corresponding bytes of the addressed memory page. the ad- dressed memory page then automatically put into an erase cycle. finally, the addressed memory page is programmed with the contents of the data buffer. all of this buffer management is handled internally, and is transparent to the user. the user is given the facility of being able to alter the contents of the memory on a byte-by-byte basis. for optimized timings, it is recommended to use the page write (pw) instru ction to write all con- secutive targeted bytes in a single sequence ver- sus using several page write (pw) sequences with each containing only a few bytes (see page write (pw) section and table 16., ac character- istics ). a fast way to modify data the page program (pp) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. this might be: ? when the designer is programming the device for the first time ? when the designer knows that the page has already been erased by an earlier page erase (pe), sector er ase (se) or bu lk erase (be) instruction. this is useful, for example, when storing a fast stream of data, having first performed the erase cycle when time was available ? when the designer knows that the only changes involve resetting bits to 0 that are still set to 1. when this method is possible, it has the additional advantage of minimising the number of unnecessary erase operations, and the extra stress incurred by each page. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted byte s in a single sequence versus using several page program (pp) se- quences with each containing only a few bytes (see page program (pp) section and table 16., ac characteristics ). polling during a write, program or erase cycle a further improvement in the write, program or erase time can be achieved by not waiting for the worst case delay (t pw , t pp , t pe , t se or t be ). the write in progress (wip) bit is provided in the sta- tus register so that the application program can monitor its value, polling it to establish when the previous cycle is complete. reset an internal power-on reset circuit helps protect against inadvertent data writes. addition protec- tion is provided by driving reset (reset ) low during the power-on process, and only driving it high when v cc has reached the correct voltage level, v cc (min). active power, standby power and deep power-down modes when chip select (s ) is low, the device is select- ed, and in the active power mode. when chip select (s ) is high, the device is dese- lected, but could remain in the active power mode until all internal cycles have completed (program, erase, write). the device then goes in to the standby power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the specific instruction (the deep power-down (dp) in-
9/43 m25pe80 struction) is executed . the device consumption drops further to i cc2 . when in this mode, only the release from deep power-down instruction is ac- cepted. all other instructions are ignored. the de- vice remains in the de ep power-down mode until the release from deep po wer-down instruction is executed. this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions. status register the status register contains two status bits that can be read by the read status register (rdsr) instruction. wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write, program or erase cycle. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. table 2. status register format note: wel and wip are volatile read-only bits (wel is set and re- set by specific instructions; wip is automatically set and re- set by the internal logic of the device). protection modes the environments where non-volatile memory de- vices are used can be very noisy. no spi device can operate correctly in the presence of excessive noise. to help combat this, the m25pe80 features the following data protection mechanisms: power on reset and an internal timer (t puw ) can provide protection against inadvertant changes while the power supply is outside the operating specification. program, erase and write instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ? power-up ? reset (reset ) driven low ? write disable (w rdi) instruction completion ? page write (pw) instruction completion ? page program (pp) instruction completion ? write to lock register (wrlr) instruction completion ? page erase (pe) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion the hardware protected mode is entered when top sector lock (tsl ) is driven low, causing the top 256 pages of memory to become read-only. when top sector lock (tsl ) is driven high, the top 256 pages of memory behave like the other pages of memory the reset (reset ) signal can be driven low to protect the contents of the memory during any critical time, not just during power-up and power-down. in addition to the low power consumption feature, the deep power-down mode offers extra software protection from inadvertant write, program and erase instructions while the device is not in active use. the software protection is managed by specific lock registers assigned to each sector and sub-sector as follows: ? each 64kb sector has a lock register ? inside sector 0 and sector 15, each 4kb sub-sector also has a lock register (in addition to the lock register at sector level) the lock registers can be read and written using the read lock register (rdlr) and write to lock register (wrlr) instructions. in each lock register two bits control the protection of each sector/sub-sector: the write lock bit and the lock down bit. ?write lock bit: the write lock bit determines whether the contents of the sector/sub-sector can be modified (using the write, program or erase instructions). when the write lock bit is set, ?1?, the se ctor/sub-sector is write protected ? any operations that attempt to change the data in the sector/sub-sector will fail. when the write lock bit is reset to ?0?, the sector/sub-sector is not write protected by the lock register, and may be modified, unless tsl is low (in which case the top sector will remain write protected). ? lock down bit: the lock down bit provides a mechanism for protecting software data from simple hacking and malicious attack. when the lock down bit is set, ?1?, further b7 b0 0 0 0 0 0 0 wel wip
m25pe80 10/43 modification to the write lock and lock down bits cannot be performed. a reset, or power-up, is required before changes to these bits can be made. when the lock down bit is reset, ?0?, the write lock and lock down bits can be changed. the write lock bit and the lock down bit are volatile and their value is reset to ?0? after a power-down or a reset. the definition of the lock register bits is given in table 8., lock register out . refer to table 3. and table 4. for details on the software protection for sectors 1 to 14 and 0 and 15, respectively. figure 6. shows the the software protection scheme. table 3. software protection truth table (sectors 1 to 14) table 4. software protection scheme truth table (sectors 0 and 15) note: 1. all other bits combinations are not-applicable. 2. for more details, refer to the description of the write to lock register (wrlr) instruction. sector lock register protection status lock down bit write lock bit 0 0 sector unprotected from program/erase/wr ite operations, protection status reversible 0 1 sector protected from program/erase/wr ite operations, protecti on status reversible 10 sector unprotected from pr ogram/erase/write operations, sector protection status cannot be c hanged except by a reset or power-up. 11 sector protected from prog ram/erase/write operations, sector protection status cannot be c hanged except by a reset or power-up. sector lock register sub-sector lock register protection status lock down bit write lock bit lock down bit write lock bit 0 0 00 current sub-sector unprotected fr om program/erase/write operations, current sub-sector protection status reversible 01 current sub-sector protected from program/erase/write operations, current sub-sector protection status reversible. 10 current sub-sector unprot ected from program/erase/write operations, current sub-sector protection stat us cannot be changed except by a reset or power-up. 11 current sub-sector protected from pr ogram/erase/write operations, current sub-sector protection stat us cannot be changed except by a reset or power-up. 1 01 all sub-sectors protected from progra m/erase/write operations, current sub- sector protection status reversible 11 all sub-sectors protected from progra m/erase/write operations, current sub- sector protection status cannot be c hanged except by a reset or power-up. 1 0 10 current sub-sector unprot ected from program/erase/write operations, all sub- sectors protection status cannot be c hanged except by a reset or power-up 11 current sub-sector protected from pr ogram/erase/write operations, all sub- sectors protection status cannot be c hanged except by a reset or power-up 111 all sub-sectors protected with their protection status cannot be changed except by a reset or power-up.
11/43 m25pe80 figure 6. software protection scheme note: 1. ld lock down bit; wl write lock bit. ai11305a sector 14 (64kbx 14) wl bit ld bit sector 0 sector lock register 14 sector lock register frozen wl bit ld bit sub-sector 0.15 lock register sub-sector 0.15 (4kb) sub-sector 0.0 (4kb) sub-sector 0.15 lock register frozen wl bit ld bit sub-sector 0.0 lock register sub-sector 0.0 lock register frozen sector 0 lock register wl bit ld bit sub-sector modify protected sub-sector modify protected sector modify protected all sub-sectors modify protected all sub-sector lock registers frozen sector 15 wl bit ld bit sub-sector 15.15 lock register sub-sector 15.15 (4kb) sub-sector 15.0 (4kb) sub-sector 15.15 lock register frozen wl bit ld bit sub-sector 15.0 lock register sub-sector 15.0 lock register frozen sector 15 lock register wl bit ld bit sub-sector modify protected sub-sector modify protected all sub-sectors modify protected all sub-sector lock registers frozen sector 1 (64kbx 14) wl bit ld bit sector lock register 1 sector lock register frozen sector modify protected
m25pe80 12/43 memory organization the memory is organized as: 4096 pages (256 bytes each). 1,048,576 bytes (8 bits each) 16 sectors (512 kbits, 65536 bytes each) each page can be individually: ? programmed (bits are programmed from 1 to 0) ? erased (bits are erased from 0 to 1) ? written (bits are changed to either 0 or 1) the device is page, sector or bulk erasable (bits are erased from 0 to 1). table 5. memory organization sector address range 15 f0000h fffffh 14 e0000h effffh 13 d0000h dffffh 12 c0000h cffffh 11 b0000h bffffh 10 a0000h affffh 9 90000h 9ffffh 8 80000h 8ffffh 7 70000h 7ffffh 6 60000h 6ffffh 5 50000h 5ffffh 4 40000h 4ffffh 3 30000h 3ffffh 2 20000h 2ffffh 1 10000h 1ffffh 0 00000h 0ffffh
13/43 m25pe80 figure 7. block diagram ai10782b s tsl control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder c d q status register 00000h fffffh 000ffh reset effffh top 256 pages can be made read-only by using the tsl pin whole memory array can be made read-only on a 64kb or 4kb basis through the lock registers
m25pe80 14/43 instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input (d) is sampled on the first rising edge of serial clock (c) after chip select (s ) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (d), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in table 6. every instruction sequence starts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. in the case of a read data bytes (read), read data bytes at higher speed (fast_read), read identification (rdid), read status register (rd- sr), or read lock regist er (rdlr) instruction, the shifted-in instruction sequence is followed by a data-out sequence. chip select (s ) can be driven high after any bit of the data-out sequence is be- ing shifted out. in the case of a page write (pw), page program (pp), write to lock register (wrlr), page erase (pe), sector erase (se), bulk erase (be), write enable (wren), write disable (wrdi), deep power-down (dp) or release from deep power- down (rdp) instruction, chip select (s ) must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select (s ) must driven high when the number of clock pulses after chip select (s ) being driven low is an exact multiple of eight. all attempts to access the memory array during a write cycle, program cycle or erase cycle are ig- nored, and the internal write cycle, program cycle or erase cycle continues unaffected. table 6. instruction set instruction description one-byte instruction code address bytes dummy bytes data bytes wren write enable 0000 0110 06h 0 0 0 wrdi write disable 0000 0100 04h 0 0 0 rdid read identification 1001 1111 9fh 0 0 1 to 3 rdsr read status register 0000 0101 05h 0 0 1 to wrlr write to lock register 1110 0101 e5h 3 0 1 rdlr read lock register 1110 1000 e8h 3 0 1 read read data bytes 0000 0011 03h 3 0 1 to fast_read read data bytes at higher speed 0000 1011 0bh 3 1 1 to pw page write 0000 1010 0ah 3 0 1 to 256 pp page program 0000 0010 02h 3 0 1 to 256 pe page erase 1101 1011 dbh 3 0 0 se sector erase 1101 1000 d8h 3 0 0 be bulk erase 1100 0111 c7h 0 0 0 dp deep power-down 1011 1001 b9h 0 0 0 rdp release from deep power-down 1010 1011 abh 0 0 0
15/43 m25pe80 write enable (wren) the write enable (wren) instruction ( figure 8. ) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set pri- or to every page write (pw), page program (pp), page erase (pe), sector erase (se), bulk erase (be) and write to lock register (wrlr) instruc- tions. the write enable (wren) instruction is entered by driving chip select (s ) low, sending the in- struction code, and then driving chip select (s ) high. figure 8. write enable (wren) instruction sequence write disable (wrdi) the write disable (wrdi) instruction ( figure 9. ) resets the write enable latch (wel) bit. the write disable (wrdi) in struction is entered by driving chip select (s ) low, sending the instruc- tion code, and then driving chip select (s ) high. the write enable latch (wel) bit is reset under the following conditions: ? power-up ? write disable (wrdi) instruction completion ? page write (pw) instruction completion ? page program (pp) instruction completion ? write to lock register (wrlr) instruction completion ? page erase (pe) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion figure 9. write disable (wrdi) instruction sequence c d ai02281e s q 2 1 34567 high impedance 0 instruction c d ai03750d s q 2 1 34567 high impedance 0 instruction
m25pe80 16/43 read identification (rdid) the read identification (r did) instruction allows the 8-bit manufacturer identification to be read, fol- lowed by two bytes of device identification. the manufacturer identification is assigned by jedec, and has the value 20h for stmicroelectronics. the device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (80h), and the memory capacity of the device in the second byte (14h). any read identification (rdid) instruction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first select ed by driving chip select (s ) low. then, the 8-bit instruction code for the in- struction is shifted in. this is followed by the 24-bit device identification, stored in the memory, being shifted out on serial data output (q), each bit be- ing shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 10. . the read identification (rdid) instruction is termi- nated by driving chip select (s ) high at any time during data output. when chip select (s ) is driven high, the device is put in the stand-by power mode. once in the stand-by power mode, the de vice waits to be se- lected, so that it can receive, decode and execute instructions. table 7. read identificati on (rdid) data-out sequence figure 10. read identification (rdid) instruction sequence and data-out sequence manufacturer identification device identification memory type memory capacity 20h 80h 14h c d s 2 1 3456789101112131415 instruction 0 ai06809b q manufacturer identification high impedance msb 15 1413 3210 device identification msb 16 17 18 28 29 30 31
17/43 m25pe80 read status register (rdsr) the read status register (rdsr) instruction al- lows the status register to be read. the status register may be read at any time, even while a program, erase or write cycle is in progress. when one of these cycles is in progress, it is rec- ommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register con- tinuously, as shown in figure 11. . the status bits of the status register are as fol- lows: wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write, program or erase cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write, program or erase instruction is accepted. figure 11. read status register (rdsr) instruction sequence and data-out sequence c d s 2 1 3456789101112131415 instruction 0 ai02031e q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
m25pe80 18/43 read data bytes (read) the device is first select ed by driving chip select (s ) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the mem- ory contents, at that address, is shifted out on se- rial data output (q), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (c). the instruction sequence is shown in figure 12. . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shift- ed out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read ) instruction is termi- nated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data out- put. any read data by tes (read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 12. read data bytes (read) instruction sequence and data-out sequence note: address bits a23 to a19 are don?t care. c d ai03748d s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
19/43 m25pe80 read data bytes at higher speed (fast_read) the device is first select ed by driving chip select (s ) low. the instruction code for the read data bytes at higher speed (fast_read) instruction is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 13. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shift- ed out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest ad- dress is reached, the address counter rolls over to 000000h, allowing the read sequence to be contin- ued indefinitely. the read data bytes at higher speed (fast_read) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driv- en high at any time during data output. any read data bytes at higher speed (fast_read) in- struction, while an erase, program or write cycle is in progress, is rejected without having any ef- fects on the cycle that is in progress. figure 13. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence note: address bits a23 to a19 are don?t care. c d ai04006 s q 23 2 1 345678910 28293031 2221 3210 high impedance instruction 24 bit address 0 c d s q 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35
m25pe80 20/43 read lock register (rdlr) the device is first select ed by driving chip select (s ) low. the instruction code for the read lock register (rdlr) instruct ion is followed by a 3- byte address (a23-a0) pointing to any location in- side the concerned sector (or sub-sector). each address bit is latched-in during the rising edge of serial clock (c). then the value of the lock reg- ister is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 14. the read lock register ( rdlr) instruction is ter- minated by driving chip select (s ) high at any time during data output. any read lock register (r dlr) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. table 8. lock register out note: 1. valid only for sector 0 and sector 15 (the value ?0? is returned for other sectors). figure 14. read lock register (rdlr) instruction sequence and data-out sequence bit bit name value function b7-b4 reserved b3 sub-sector lock down (1) ?1? the write lock and lock down bits cannot be changed once a ?1? is written to the lock down bit it cannot be cleared to ?0? except by a reset or power-up. ?0? the write lock and lock down bits can be changed by writing new values to them. (default value). b2 sub-sector write lock (1) ?1? write, program and erase operations in this sub-sector will not be executed. the memory contents will not be changed. ?0? write, program and erase operations in this sub-sector are executed and will modify the sub-sector contents. (default value). b1 sector lock down ?1? the write lock and lock down bits cannot be changed. once a ?1? is written to the lock down bit it c annot be cleared to ?0?, except by a reset or power-up. ?0? the write lock and lock down bits can be changed by writing new values to them. (default value). b0 sector write lock ?1? write, program and erase operations in this sector will not be executed. the memory contents will not be changed. ?0? write, program and erase operations in this sector are executed and will modify the sector contents. (default value). c d ai10783 s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 0 high impedance lock register out instruction 24-bit address 0 msb msb 2 39
21/43 m25pe80 page write (pw) the page write (pw) instruction allows bytes to be written in the memory. before it can be accept- ed, a write enable (wren) instruction must previ- ously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page write (pw) instruction is entered by driving chip select (s ) low, followed by the in- struction code, three address bytes and at least one data byte on serial data input (d). the rest of the page remains unchanged if no power failure occurs during this write cycle. the page write (pw) instruction performs a page erase cycle even if only one byte is updated. if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data exceeding the ad- dressed page boundary roll over, and are written from the start address of the same page (the one whose 8 least significant address bits (a7-a0) are all zero). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 15. if more than 256 bytes are sent to the device, pre- viously latched data are discarded and the last 256 data bytes are guaranteed to be written correctly within the same page. if less than 256 data bytes are sent to device, they are correctly written at the requested addresses without having any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page write (pw) inst ruction to write all con- secutive targeted bytes in a single sequence ver- sus using several page write (pw) sequences with each containing only a few bytes chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page write (pw) instruction is not executed. as soon as chip select (s ) is driven high, the self- timed page write cycle (whose duration is t pw ) is initiated. while the page wr ite cycle is in progress, the status register may be read to check the val- ue of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page write cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a page write (pw) instruction applied to a page that is hardware or software protected is not exe- cuted. any page write (pw) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 15. page write (pw) instruction sequence note: 1. address bits a23 to a19 are don?t care 2. 1 n 256 c d ai04045 s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte n 765432 0 1 msb msb msb msb msb
m25pe80 22/43 page program (pp) the page program (pp) in struction allows bytes to be programmed in the memory (changing bits from 1 to 0, only). before it can be accepted, a write enable (wren) inst ruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page program (pp) instruction is entered by driving chip select (s ) low, followed by the in- struction code, three address bytes and at least one data byte on serial data input (d). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data exceeding the ad- dressed page boundary roll over, and are pro- grammed from the start address of the same page (the one whose 8 least significant address bits (a7-a0) are all zero). chip select (s ) must be driv- en low for the entire duration of the sequence. the instruction sequence is shown in figure 16. if more than 256 bytes are sent to the device, pre- viously latched data are discarded and the last 256 data bytes are guaranteed to be programmed cor- rectly within the same page. if less than 256 data bytes are sent to device, they are correctly pro- grammed at the requested addresses without hav- ing any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted byte s in a single sequence versus using several page program (pp) se- quences with each containing only a few bytes (see table 16., ac characteristics ). chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (s ) is driven high, the self- timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self- timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page that is hardware or software protected is not exe- cuted. any page program (pp) instruction, while an erase, program or write cycle is in progress, is re- jected without having any effects on the cycle that is in progress. figure 16. page program (pp) instruction sequence note: 1. address bits a23 to a19 are don?t care 2. 1 n 256 c d ai04044 s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte n 765432 0 1 msb msb msb msb msb
23/43 m25pe80 write to lock register (wrlr) the write to lock register (wrlr) instruction al- lows bits to be changed in the lock registers. be- fore it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the write to lock regist er (wrlr) instruction is entered by driving chip select (s ) low, followed by the instruction code, three address bytes (pointing to any address in the targeted sector/ sub-sector) and one data byte on serial data input (d). the instruction sequence is shown in figure 17. chip select (s ) must be driven high after the eighth bit of the data byte has been latched in, oth- erwise the write to lock register (wrlr) instruc- tion is not executed. when the write to lock register (wrlr) instruc- tion has been successfully executed, the write en- able latch (wel) bit is reset after a delay time less than t shsl minimum value. any write to lock regist er (wrlr) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 17. write to lock register (wrlr) instruction sequence table 9. lock register in note: 1. b6-b4 and b1-b0 must be reset to ?0?. 2. b6-b2 must be reset to ?0?. sector bit value all sectors except for sector 0 and sector 15 b7-b2 ?0? b1 sector lock down bit value (refer to table 8. ) b0 sector write lock bit value (refer to table 8. ) sector 0 sector 15 b7 ?1? only b3 and b2 are taken into account to modify the sub- sector write lock and lock down bits (1) ?0? only b1 and b0 are taken into account to modify the sector write lock and lock down bits (2) b3 sub-sector lock down bit value (refer to table 8. ) b2 sub-sector write lock bit value (refer to table 8. ) b1 sector lock down bit value (refer to table 8. ) b0 sector write lock bit value (refer to table 8. ) ai10784 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 lock register in 39 msb msb
m25pe80 24/43 protection always prevails: when the lock down bit of sector 0 or sector 15 is set to ?1?. ? if the lock down bit of sector 0 is ?1?, all the lock down bits of the sub-sectors in sector 0 are forced to ?1?. ? if the lock down bit of sector 15 is ?1?, all the lock down bits of the sub-sectors in sector 15 are forced to ?1? when the write lock bit of sector 0 or sector 15 is set to ?1?. ? if the write lock bit of sector 0 is ?1?, the write lock bits of all the sub-sectors in sector 0 are forced to ?1? (even if their lock down bits are set to ?1?). ? if the write lock bit of sector 15 is ?1?, the write lock bits of all the sub-sectors in sector 15 are forced to ?1? (even if their lock down bits are set to ?1?). when the write lock bit of sector 0 or sector 15 is reset to ?0?. ? if the write lock bit of sector 0 is ?0?, all the sub-sectors in sector 0 whose lock down bit is ?0? have their write lock bits forced to ?0?. ? if the write lock bit of sector 15 is ?0?, all the sub-sectors in sector 15 whose lock down bit is ?0? have their write lock bits forced to ?0?. when the write lock bit of any sector or sub- sector is set to ?1?, any instruction that may modify the contents of this sector or sub- sector will be rejected (including sector erase and bulk erase). note that when the wrlr instruction acts both on write lock (wl) and lock down (ld) bits, it firstly programs the wl bit, and then the ld bit. as an example, if a sub-sector lock register set- tings are xxxx0101b and a wrlr instruction is is- sued with a lock register in data set to 00000010b: 1. the sector wl bit is first set to ?0? (and all sub- sectors that are not locked-down will have their wl bit reset to ?0?). 2. the sector ld bit and all sub-sectors ld bits are set to ?1?. in this case, the final value of the above sub-sector lock register is xxxx1010b.
25/43 m25pe80 page erase (pe) the page erase (pe) instruction sets to 1 (ffh) all bits inside the chosen page. before it can be ac- cepted, a write enable (wren) instruction must previously have been exec uted. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page erase (pe) instruction is entered by driving chip select (s ) low, followed by the in- struction code, and three address bytes on serial data input (d). any address inside the page is a valid address for the page erase (pe) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 18. . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the page erase (pe) instruc- tion is not executed. as soon as chip select (s ) is driven high, the self-timed page erase cycle (whose duration is t pe ) is initiated. while the page erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page erase cycle, and is 0 when it is complete d. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a page erase (pe) instruction applied to a page that is hardware or software protected is not exe- cuted. any page erase (pe) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 18. page erase (pe) instruction sequence note: address bits a23 to a19 are don?t care. 24 bit address c d ai04046 s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
m25pe80 26/43 sector erase (se) the sector erase (se) inst ruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decod- ed, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (s ) low, followed by the in- struction code, and three address bytes on serial data input (d). any address inside the sector (see table 5. ) is a valid address for the sector erase (se) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 19. . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) in- struction is not executed. as soon as chip select (s ) is driven high, the self -timed sector erase cy- cle (whose duration is t se ) is initiated. while the sector erase cycle is in progress, the status reg- ister may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is comple ted. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a sector that contains a page that is hardware or software protected is not executed. any sector erase (se) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 19. sector erase (se) instruction sequence note: address bits a23 to a19 are don?t care. 24 bit address c d ai03751d s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
27/43 m25pe80 bulk erase (be) the bulk erase (be) instruction sets all bits to 1 (ffh). before it can be accepted, a write enable (wren) instruction must pr eviously have been ex- ecuted. after the write en able (wren) instruction has been decoded, the device sets the write en- able latch (wel). the bulk erase (be) instruction is entered by driv- ing chip select (s ) low, followed by the instruction code on serial data input (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 20. chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the bulk eras e instruction is not exe- cuted. as soon as chip select (s ) is driven high, the self-timed bulk erase cycle (whose duration is t be ) is initiated. while th e bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self- timed bulk erase cycle, and is 0 when it is com- pleted. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. any bulk erase (be) inst ruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. a bulk erase (be) instruction is ignored if at least one sector or sub-sector is write-protect- ed (hardware or software protection). figure 20. bulk erase (be) instruction sequence c d ai03752d s 2 1 34567 0 instruction
m25pe80 28/43 deep power-down (dp) executing the deep powe r-down (dp) instruction is the only way to put the device in the lowest con- sumption mode (the deep power-down mode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. driving chip select (s ) high deselect s the device, and puts the device in the standby mode (if there is no internal cycle current ly in progress). but this mode is not the deep power-down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) instruction, subsequently reducing the standby current (from i cc1 to i cc2 , as specified in table 15. ). once the device has entered the deep power- down mode, all instructions are ignored except the release from deep powe r-down (rdp) instruc- tion. issuing the release from deep power-down (rdp) instruction will cause the device to exit the deep power-down mode. the deep power-down m ode automatically stops at power-down, and the device always powers-up in the standby mode. the deep power-down (dp) instruction is entered by driving chip select (s ) low, followed by the in- struction code on serial data input (d). chip se- lect (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 21. . chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the deep po wer-down (dp) instruc- tion is not executed. as soon as chip select (s ) is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down (dp) instruction, while an erase, program or write cycle is in progress, is re- jected without having any effects on the cycle that is in progress. figure 21. deep power-down (dp) instruction sequence c d ai03753d s 2 1 34567 0 t dp deep power-down mode stand-by mode instruction
29/43 m25pe80 release from deep power-down (rdp) once the device has entered the deep power- down mode, all instructions are ignored except the release from deep powe r-down (rdp) instruc- tion. executing this instruction takes the device out of the deep power-down mode. the release from deep power-down (rdp) in- struction is entered by driving chip select (s ) low, followed by the instruction code on serial data in- put (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 22. . the release from deep power-down (rdp) in- struction is terminated by driving chip select (s ) high. sending additional clock cycles on serial clock (c), while chip select (s ) is driven low, cause the instruction to be rejected, and not exe- cuted. after chip select (s ) has been driven high, fol- lowed by a delay, t rdp , the device is put in the standby mode. chip select (s ) must remain high at least until this period is over. the device waits to be selected, so that it can receive, decode and execute instructions. any release from deep power-down (rdp) in- struction, while an erase, program or write cycle is in progress, is rejected without having any ef- fects on the cycle that is in progress. figure 22. release from deep power-down (rdp) instruction sequence c d ai06807 s 2 1 34567 0 t rdp stand-by mode deep power-down mode q high impedance instruction
m25pe80 30/43 power-up and power-down at power-up and power-down, the device must not be selected (that is chip select (s ) must follow the voltage applied on v cc ) until v cc reaches the correct value: ?v cc (min) at power-up, and then for a further delay of t vsl ?v ss at power-down usually a simple pull-up resistor on chip select (s ) can be used to ensure safe and proper power-up and power-down. to avoid data corruption and inadvertent write op- erations during power-up, a power on reset (por) circuit is included. the logic inside the de- vice is held reset while v cc is less than the power on reset (por) threshold voltage, v wi ? all oper- ations are disabled, and the device does not re- spond to any instruction. moreover, the device ignores all write enable (wren), page write (pw) , page program (pp), page erase (pe), sector erase (se), bulk erase (be) and write to lock register (wrlr) instruc- tions until a time delay of t puw has elapsed after the moment that v cc rises above the v wi thresh- old. however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc (min). no write, program or erase instructions should be sent until the later of: ?t puw after v cc passed the v wi threshold ?t vsl after v cc passed the v cc (min) level these values are specified in table 10. . if the delay, t vsl , has elapsed, after v cc has risen above v cc (min), the device can be selected for read instructions even if the t puw delay is not yet fully elapsed. as an extra protection, the reset (reset ) signal could be driven low for the whole duration of the power-up and power-down phases. at power-up, the device is in the following state: ? the device is in the standby mode (not the deep power-down mode). ? the write enable latch (wel) bit is reset. normal precautions must be taken for supply rail decoupling, to stabilize the v cc supply. each de- vice in a system should have the v cc rail decou- pled by a suitable capacitor close to the package pins. (generally, this capacitor is of the order of 0.1f). at power-down, when v cc drops from the operat- ing voltage, to below th e power on reset (por) threshold voltage, v wi , all operations are disabled and the device does not respond to any instruc- tion. (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, some data corruption can result.) figure 23. power-up timing v cc ai04009c v cc (min) v wi reset state of the device chip selection not allowed program, erase and write commands are rejected by the device tvsl tpuw time read access allowed device fully accessible v cc (max)
31/43 m25pe80 table 10. power-up timing and v wi threshold note: 1. these parameters are characterized only, over the temperature range ?40c to +85c. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). all usable status register bits are 0. symbol parameter min. max. unit t vsl 1 v cc (min) to s low 30 s t puw 1 time delay before the first write, program or erase instruction 1 10 ms v wi 1 write inhibit voltage 1.5 2.5 v
m25pe80 32/43 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to abso lute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 11. absolute maximum ratings note: 1. compliant with jedec std j-std-020c (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 ? , r2=500 ? ) symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering see note 1 c v io input and output voltage (with respect to ground) ?0.6 4.0 v v cc supply voltage ?0.6 4.0 v v esd electrostatic discharge vo ltage (human body model) 2 ?2000 2000 v
33/43 m25pe80 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 12. operating conditions table 13. ac measurement conditions note: output hi-z is defined as the point where data out is no longer driven. figure 24. ac measurement i/o waveform table 14. capacitance note: sampled only, not 100% tested, at t a =25c and a frequency of 20 mhz. symbol parameter min. max. unit v cc supply voltage 2.7 3.6 v t a ambient operating temperature ?40 85 c symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timi ng reference voltages 0.3v cc to 0.7v cc v symbol parameter test condition min . max . unit c out output capacitance (q) v out = 0v 8 pf c in input capacitance (other pins) v in = 0v 6 pf ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
m25pe80 34/43 table 15. dc characteristics symbol parameter test condition (in addition to those in table 12. ) min. max. unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current (standby and reset modes) s = v cc , v in = v ss or v cc 50 a i cc2 deep power-down current s = v cc , v in = v ss or v cc 10 a i cc3 operating current (fast_read) c = 0.1v cc / 0.9.v cc at 50mhz, q = open 6ma i cc4 operating current (pw) s = v cc 15 ma i cc5 operating current (se) s = v cc 15 ma v il input low voltage ? 0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = ?100 av cc ?0.2 v
35/43 m25pe80 table 16. ac characteristics note: 1. t ch + t cl must be greater than or equal to 1/ f c 2. value guaranteed by characterization, not 100% tested in production. 3. when using pp and pw instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. test conditions specified in table 12. and table 13. symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, rdlr, pw, pp, wrlr, pe, se, dp, rdp, wren, wrdi, rdsr d.c. 50 mhz f r clock frequency for read instructions d.c. 20 mhz t ch (1) t clh clock high time 9 ns t cl (1) t cll clock low time 9 ns clock slew rate 2 (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 9 ns t chsl s not active hold time (relative to c) 9 ns t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 9 ns t shch s not active setup time (relative to c) 9 ns t shsl t csh s deselect time 100 ns t shqz (2) t dis output disable time 8 ns t clqv t v clock low to output valid 8 ns t clqx t ho output hold time 0 ns t thsl top sector lock setup time 50 ns t shtl top sector lock hold time 100 ns t dp (2) s to deep power-down 3 s t rdp (2) s high to standby mode 30 s t pw (3) page write cycle time (256 bytes) 11 25 ms page write cycle time (n bytes) 10.2 + n * 0.8/256 t pp (3) page program cycle time (256 bytes) 1.2 5ms page program cycle time (n bytes) 0.4 + n * 0.8/256 t pe page erase cycle time 10 20 ms t se sector erase cycle time 1 5 s t be bulk erase cycle time 16 60 s
m25pe80 36/43 figure 25. serial input timing figure 26. top sector lock setup and hold timing c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c d s q high impedance tsl tthsl tshtl ai07439b
37/43 m25pe80 figure 27. output timing c q ai01449e s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv
m25pe80 38/43 table 17. reset timings note: 1. value guaranteed by characterization, not 100% tested in production. figure 28. reset ac waveforms test conditions specified in table 12. and table 13. symbol alt. parameter conditions min. typ. max. unit t rlrh (1) t rst reset pulse width 10 s t rhsl t rec reset recovery time after any operation except for pw, pp, pe, se and be 30 s after pw, pp, pe, se and be operations (1) 300 s t shrh chip select high to reset high chip should have been deselected before reset is de-asserted 10 ns ai06808 reset trlrh s trhsl tshrh
39/43 m25pe80 package mechanical figure 29. mlp8, 8-lead very thin dual flat package no lead, 6x5mm, package outline note: drawing is not to scale. table 18. mlp8, 8-lead very thin dual flat package no lead, 6x5mm, package mechanical data symbol millimeters inches typ. min. max. typ. min. max. a 0.85 1.00 0.0335 0.0394 a1 0.00 0.05 0.0000 0.0020 a2 0.65 0.0256 a3 0.20 0.0079 b 0.40 0.35 0.48 0.0157 0.0138 0.0189 d 6.00 0.2362 d1 5.75 0.2264 d2 3.40 3.20 3.60 0.1339 0.1260 0.1417 e 5.00 0.1969 e1 4.75 0.1870 e2 4.00 3.80 4.20 0.1575 0.1496 0.1654 e 1.27 0.0500 l 0.60 0.50 0.75 0.0236 0.0197 0.0295 12 12 d e vdfpn-01 a2 a a3 a1 e1 d1 e e2 d2 l b
m25pe80 40/43 figure 30. so8 wide ? 8 lead plastic small outline, 208 mils body width, package outline note: drawing is not to scale. table 19. so8 wide ? 8 lead plastic small outline, 208 mils body width, mechanical data symbol millimeters inches typ min max typ min max a 2.03 0.080 a1 0.10 0.25 0.004 0.010 a2 1.78 0.070 b 0.35 0.45 0.014 0.018 c 0.20 ? ? 0.008 ? ? cp 0.10 0.004 d 5.15 5.35 0.203 0.211 e 5.20 5.40 0.205 0.213 e1.27? ?0.050? ? h 7.70 8.10 0.303 0.319 l 0.50 0.80 0.020 0.031 a010010 n8 8 so-b e n cp b e a2 d c l a1 h a 1
41/43 m25pe80 part numbering table 20. ordering information scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. example: m25pe80 ? v mp 6 t p device type m25pe = page-erasable serial flash memory device function 80 = 8mbit (1mb x 8) operating voltage v = v cc = 2.7 to 3.6v package mw = so8 (208 mils width) mp = vdfpn8 6x5mm (mlp8) device grade 6 = industrial: device tested with standard test flow over ?40 to 85 c option blank = standard packing t = tape and reel packing plating technology blank = standard snpb plating p or g = rohs compliant
m25pe80 42/43 revision history table 21. document revision history date version description of revision 24-nov-2004 0.1 f irst issue. 07-dec-2004 0.2 4kb software protection granularity extended to sector 15. 10-may-2005 0.3 so16w package removed, so8w package added. end timing line of t shqz modified in figure 27., output timing . plating technology options modified in table 20., ordering information scheme . minor text changes. ta bl e s 3 and 4 and figure 6. for details on the software protection scheme. 25-jul-2005 0.4 lock register programming sequence detailed in section write to lock register (wrlr) . sections an easy way to modify data , a fast way to modify data , page write (pw) and page program (pp) , updated to explain when using page write and page program instructions. bulk erase cycle time (t be ), page write cycle time (t pw ) and page program cycle time (t pp ) updated in table 16., ac characteristics . 24-aug-2005 1.0 version number updated for internet. no document changes. 25-aug-2005 2.0 document status updated to preliminary data.
43/43 m25pe80 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. ecopack is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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